My main interest is a fusion of the device, circuit, and system co-design areas. This integrated area has gained a major role in the current development of new hardware in machine learning applications. I received my B.Sc. and M.Sc. degrees from KAIST, South Korea. There, I had the pleasure to work with Professor Yang-Kyu Choi. While in Korea, I focused my education and research in semiconductor devices. Currently, I'm at my last semester under advisement of Professor Chenming Hu and also a member of the Professor Sayeef Salahuddin's group. While in Berkeley, I have been expanding my education and research from device to circuit and system areas. I have been developing the new industry standard compact models (BSIM models) for FinFETs and UTBSOI devices. Another part of my research is related to Negative Capacitance FinFETs, where I have developed numerical simulations and compact models for these devices. Currently we are evaluating the impact of these devices at circuit and system levels. I am also passionate in teaching/education, specifically on hardware design, where I have had experience in developing and teaching a course in UC Berkeley.
Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design
Core Compact Models for Multiple-Gate Field-Effect-Transistors
Research code, DeCal course, etc.
Hi!, I am Juan Pablo Duarte I am currently in my last semester of my PhD and looking for new oportunities in the industry and academia. Please feel free to contact me.
Ph.D. Electrical Engineering and Computer Sciences
Thesis: Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design. Advisor: Professor Chenming Hu
M.S. Electrical Engineering
Thesis: Core Compact Models for Multiple-Gate Field-Effect-Transistors. Advisor: Professor Yang-Kyu Choi.
B.S. Electrical Engineering
Technology aware hardware design for machine learning: Modeling, simulation and design of new hardware architectures for machine learning applications using advanced memory and logic devices.
Negative-Capacitance Transistors: Numerical simulation, compact modeling, and circuit evaluation.
Mathematical Compact Model for Independent Gate Transistors (BSIM-IMG): A new core model for UTBSOI transistors including back-gate inversion was developed considering good speed and convergence capabilities.
Unified Compact Model of Advanced CMOS (BSIM-CMG): A comprehensive mathematical model was developed for FinFET transistors with complex fin structures and new materials was developed for industrial applications.
Main Lectuer. DeCal Course: Hardware Makers. Students learned how to create hardware with wifi/bluetooth connections of several prototyping boards, sensors, actuators, and additional electronics components.
Graduate Student Instructor. Designing Information Devices and Systems II (Fall/Spring): I was a Lab Instructor where students focused on the fundamentals of designing and building modern information devices and systems that interface with the real world.
Summer Research Intern. Complementary Metal-Oxide Semiconductor (CMOS) Device intern: Measurement and characterization of III-V transistors.
Lecturer. Digital System Lab (Laboratorio de Sistemas Digitales), Advanced Design of Digital Systems (Diseno Avanzado de Sistemas Digitales), Physical Electronics (Fisica Electronica)
Graduate Research Assistant. Exploration of Nano-Fusion Memory Technology. Development of novel 3D stacked devices and core materials for the next generation flash memory. Terabit Nonvolatile Memory Development. Trans-scale convergence technology for nano devices. Underlap field effect transistor modeling for biosensor applications (during undergraduate).
TA: Introduccion a la Fisica
Dissertation: "Negative Capacitance Transistors: Numerical Simulation, Compact Modeling and Circuit Evaluation"
Compact Models of Negative-Capacitance FinFETs: lumped and distributed charge models
Unified CMOS Compact Model for Advanced Transistor Structures (Review Talk)
Modeling Independent Multi-Gate MOSFET (Invited Talk)
Analog and RF bulk CMOS Compact Model (Review Talk)
BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit Design (Invited Talk)
BSIM-CMG and BSIM-IMG models (Review Talk)
Multi-Gate FET Modeling (Invited Talk)
FinFET Compact Modeling Using MAPP/MDE: Implementation and Parameter Extraction (Invited Talk)
Unified FinFET Compact Model: Modeling Trapezoidal Triple-Gate FinFETs (Best Student Paper)
Unified FinFET Compact Model
SISPAD 2013. Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.
International graduate student scholarship. Korea Advanced Institute of Science and Technology.
International undergraduate student scholarship. Korea Advanced Institute of Science and Technology.
Highest undergraduate GPA. Universidad Federico Santa Maria
Throughout my education, starting from Chile, later doing my Undergraduate and Master in South Korea, to later finishing my PhD at Berkeley, I have been part of several multicultural research teams. Language skills have played a key role in my experience.
Feel free to email, call, or visit me!
550 Sutardja Dai Hall, MC1764, Berkeley, CA, USA
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