About Me

My main interest is a fusion of the device, circuit, and system co-design areas. This integrated area has gained a major role in the current development of new hardware in machine learning applications. I received my B.Sc. and M.Sc. degrees from KAIST, South Korea. There, I had the pleasure to work with Professor Yang-Kyu Choi. While in Korea, I focused my education and research in semiconductor devices. Currently, I'm at my last semester under advisement of Professor Chenming Hu and also a member of the Professor Sayeef Salahuddin's group. While in Berkeley, I have been expanding my education and research from device to circuit and system areas. I have been developing the new industry standard compact models (BSIM models) for FinFETs and UTBSOI devices. Another part of my research is related to Negative Capacitance FinFETs, where I have developed numerical simulations and compact models for these devices. Currently we are evaluating the impact of these devices at circuit and system levels. I am also passionate in teaching/education, specifically on hardware design, where I have had experience in developing and teaching a course in UC Berkeley.

Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design

PhD's Thesis

Core Compact Models for Multiple-Gate Field-Effect-Transistors

MS's Thesis

Research code, DeCal course, etc.

GitHub

Hi!, I am Juan Pablo Duarte I am currently in my last semester of my PhD and looking for new oportunities in the industry and academia. Please feel free to contact me.

  • Name: Juan Pablo Duarte
  • Email: jpduarte eecs.berkeley.edu
  • Phone: (510) 506 0311
  • Website: eecs.berkeley.edu/~jpduarte
  • Interests: Mathematical modeling and simulation. Technology aware hardware design for machine learning algorithms. Semiconductor technology device/circuit/system design, modeling, simulation, and characterization. Planar, FinFETs, and UTBSOI CMOS devices. ASIC and VLSI Design and Optimization. Negative-Capacitance FETs. Ferroelectric-CMOS memories. Biosensor design and characterization.
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Education
2012-2018
University of California, Berkeley

Ph.D. Electrical Engineering and Computer Sciences

Thesis: Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design. Advisor: Professor Chenming Hu

2010-2012
Korea Advanced Institute of Science and Technology

M.S. Electrical Engineering

Thesis: Core Compact Models for Multiple-Gate Field-Effect-Transistors. Advisor: Professor Yang-Kyu Choi.

2007-2010
Korea Advanced Institute of Science and Technology

B.S. Electrical Engineering

2005-2006
Universidad Santa Marica, Valparaiso, Chile

Electronic Engineering

Experience
2018-present
University of California, Berkeley

Technology aware hardware design for machine learning: Modeling, simulation and design of new hardware architectures for machine learning applications using advanced memory and logic devices.

2015-2017
University of California, Berkeley

Negative-Capacitance Transistors: Numerical simulation, compact modeling, and circuit evaluation.

2015-2017
University of California, Berkeley

Mathematical Compact Model for Independent Gate Transistors (BSIM-IMG): A new core model for UTBSOI transistors including back-gate inversion was developed considering good speed and convergence capabilities.

2012-2015
University of California, Berkeley

Unified Compact Model of Advanced CMOS (BSIM-CMG): A comprehensive mathematical model was developed for FinFET transistors with complex fin structures and new materials was developed for industrial applications.

2017
University of California, Berkeley

Main Lectuer. DeCal Course: Hardware Makers. Students learned how to create hardware with wifi/bluetooth connections of several prototyping boards, sensors, actuators, and additional electronics components.

2016
University of California, Berkeley

Graduate Student Instructor. Designing Information Devices and Systems II (Fall/Spring): I was a Lab Instructor where students focused on the fundamentals of designing and building modern information devices and systems that interface with the real world.

2015
Thomas J. Watson Research Center, IBM, Yorktown, NY

Summer Research Intern. Complementary Metal-Oxide Semiconductor (CMOS) Device intern: Measurement and characterization of III-V transistors.

2012
Universidad Federico Santa Maria, Valparaiso, Chile

Lecturer. Digital System Lab (Laboratorio de Sistemas Digitales), Advanced Design of Digital Systems (Diseno Avanzado de Sistemas Digitales), Physical Electronics (Fisica Electronica)

2009-2012
Korea Advanced Institute of Science and Technology

Graduate Research Assistant. Exploration of Nano-Fusion Memory Technology. Development of novel 3D stacked devices and core materials for the next generation flash memory. Terabit Nonvolatile Memory Development. Trans-scale convergence technology for nano devices. Underlap field effect transistor modeling for biosensor applications (during undergraduate).

2006
Universidad Federico Santa Maria, Valparaiso, Chile

TA: Introduccion a la Fisica

Talks
2017
University of California, Berkeley

Dissertation: "Negative Capacitance Transistors: Numerical Simulation, Compact Modeling and Circuit Evaluation"

2016
IEDM, San Francisco

Compact Models of Negative-Capacitance FinFETs: lumped and distributed charge models

2016
GRC Technology Transfer e-Workshop

Unified CMOS Compact Model for Advanced Transistor Structures (Review Talk)

2016
TechConnect World Innovation - WCM, Maryland, USA

Modeling Independent Multi-Gate MOSFET (Invited Talk)

2015
SRC Review, University of Texas at Dallas

Analog and RF bulk CMOS Compact Model (Review Talk)

2015
ESSCIRC, Graz, Austria

BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit Design (Invited Talk)

2015
SRC Review, Purdue University

BSIM-CMG and BSIM-IMG models (Review Talk)

2014
Network for Computational Nanotechnology NEEDS, Berkeley

Multi-Gate FET Modeling (Invited Talk)

2013
Network for Computational Nanotechnology NEEDS, Massachusetts Institute of Technology

FinFET Compact Modeling Using MAPP/MDE: Implementation and Parameter Extraction (Invited Talk)

2013
SISPAD, Glasgow, Scotland

Unified FinFET Compact Model: Modeling Trapezoidal Triple-Gate FinFETs (Best Student Paper)

2013
SRC Review, UCSB

Unified FinFET Compact Model

Awards

Best Student Paper Award

SISPAD 2013. Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.

Graduate Scholarship

International graduate student scholarship. Korea Advanced Institute of Science and Technology.

Undergraduate Scholarship

International undergraduate student scholarship. Korea Advanced Institute of Science and Technology.

Academic Merit Award

Highest undergraduate GPA. Universidad Federico Santa Maria

Skills
multiline_chart

Modeling and Simulation

developer_board

ASIC/VLSI Design and Optimization

sim_card

Circuit Simulation

memory

CMOS Technology

Python

Verilog

devices_other

Hardware

Sensors

Algorithms

Language Skills

Throughout my education, starting from Chile, later doing my Undergraduate and Master in South Korea, to later finishing my PhD at Berkeley, I have been part of several multicultural research teams. Language skills have played a key role in my experience.

Spanish (Fluent)
English (Advanced)
Korean (Basic)
Indonesian (Basic)
Portfolio (Under Contruction)
Contact Me

Feel free to email, call, or visit me!

jpduarte eecs.berkeley.edu

+1 510 506 0311

550 Sutardja Dai Hall, MC1764, Berkeley, CA, USA